Communications interfaces for both communications between processors and memory and for communication with input/output devices have traditionally been constrained by the physical characteristics of the devices which the interface interconnects. For example, limitations in physical connections (e.g input/output pins) have caused interface architectures to maximize throughput in the connection constrained environment. Thus, these communication architectures have sought to reduce the number of buses and, therefore, the number of connections required while still providing acceptable data throughput.
Examples of previous architectures for input/output and memory access include those described in IBM Technical Disclosure Bulletin ("IBM TDB") Vol. 32, No. 4A, September 1989. As described in the IBM TDB, throughput to both memory and I/O devices is increased by duplicating both address, data and control buses. As described in the IBM TDB, a single processor controls both buses and only a single operation can occur on either bus. Thus, the throughput is increased but at the expense of doubling the number of connections required between the processor and the memory and I/O devices. Furthermore, only a single processor is described as initiating operations.
U.S. Pat. No. 5,278,957 ("the '957 patent") to Chan describes a data transfer circuit where 100% data integrity is not required. The '957 patent describes a circuit for transferring data from one bus system to another bus system. The two bus systems perform operations with no handshaking for write operations or a minimum of handshaking for read operations. Accordingly, the data transfer circuit of the '957 patent is unsuitable for memory access or input/output where data integrity is required. For example, the system of the '957 patent may be unsuitable for operations such as fetching instructions from memory. Furthermore, the system of the '957 patent does not indicate how read or write operations are initiated or how read or write addressing is carried out.
Additionally, U.S. Pat. No. 5,060,145 ("the '145 patent") to Scheuneman et al. describes a memory access system which allows for one transfer, either read or write, per cycle. The '145 patent describes separate buses for reads and writes and which for each cycle of a read or write operation have a corresponding address cycle on an address bus. Thus, for every cycle of a read or write operation there is a corresponding address cycle. While the system of the '145 patent does allow for some pipelining of transfers it does not allow for multiple cycle transfers of opposite directions based upon a single address placed on the address bus. Thus, the data throughput of the system of the '145 patent may be limited by the address bus data rate. Accordingly, the system of the '145 patent does not achieve as high a degree of throughput as is theoretically possible.
As the density of integrated circuits increased, more and more functions of a processing system have been incorporated in a single integrated circuit. However, the same communications systems utilized for I/O bound multiple component systems, such as those systems described above, have typically been incorporated into single integrated devices. With the increased integration of devices, a different set of constraints are placed on communications interfaces. For example, even with integrated devices there is still a limitation on the number of "buses" which may be implemented within a single integrated circuit, as circuit "real estate" may limit the ability to interconnect functions within a single device. Accordingly, there still exists a need for new communication systems which may exploit the advantages of increased integration of functions in a single device.